1. Field of the Invention
This invention relates to a buffer circuit and, more particularly, to a high impedance circuit for a signal processing circuit.
2. Description of the Prior Art
As well-known buffer circuits of the type noted above, there are an emitter follower circuit as shown in FIG. 1, consisting of NPN transistors 1 and 2, and a source follower circuit as shown in FIG. 2, consisting of a field-effect transistor 3 and resistors R1 and R2. In these prior art buffer circuits, however, part of the input signal principally flows as base current or to a bias resistor. Therefore, the circuit's input impedance cannot be freely increased. Where the buffer circuit is used in a clamp circuit, a sample/hold circuit or a drive circuit for driving a capacitive load, therefore, waveform distortions are liable to result due to the fact that the input impedance cannot be freely increased. FIG. 3 shows a circuit which is disclosed in "IEEE Journal of Solid-State Circuit", Vol. SC-16, No. 6, December 1981, pp. 748-749. This circuit uses transistors 11 to 14 respectively having high current amplification factors h.sub.fe1, h.sub.fe2, h.sub.fe3 and f.sub.fe4. When h.sub.fe1 .congruent.h.sub.fe2 .congruent.h.sub.fe3 .congruent.h.sub.fe4 the base currents i.sub.B1 .congruent.i.sub.B2 in the respective transistors 11 and 12 are i.sub.B1 .congruent.i.sub.B2. This means that the base currents for driving the transistors 11 and 12 need not be supplied from a signal source. To be more specific, in the circuit of FIG. 3 an input signal V.sub.IN from an input signal terminal 10 is applied to the common base of first PNP and NPN transistors 11 and 12. The first PNP transistor 11 has its collector grounded and its emitter connected to the collector of a second PNP transistor 14. The NPN transistor 12 has the emitter connected to a signal output terminal 18 and also connected to a constant current source 15 and the collector connected to the emitter of a second NPN transistor 13. The second PNP and NPN transistors 14 and 13 have a common base. The emitter of the second PNP transistor 14 and the collector of the second NPN transistor 13 are commonly connected to a power supply terminal 17.
In the above circuit, the collector currents I.sub.1 to I.sub.4 through the respective transistors 11 to 14 are given as EQU I.sub.1 =h.sub.fe1 .multidot.i.sub.B1, EQU I.sub.2 =h.sub.fe2 .multidot.i.sub.B2, EQU I.sub.3 =h.sub.fe3 .multidot.i.sub.B3,
and EQU I.sub.4 =h.sub.fe4 .multidot.i.sub.B4
where i.sub.B1, i.sub.B2, i.sub.B3 and i.sub.B4 are respectively the base currents through the transistors 11 to 14 and h.sub.fe1, h.sub.fe2, h.sub.fe3 and h.sub.fe4 are respectively the current amplification factors of the transistors 11 to 14. The case current i.sub.B2 in the first NPN transistor 12, which has its emitter connected to the constant current source 15, is given as ##EQU1## I is the current in the constant current source 15.
The base current i.sub.B3 in the second NPN transistor 13, which has its emitter connected to the collector of the first NPN transistor 12, is given as ##EQU2##
This means that the base current i.sub.B4 flowing in the second PNP transistor 14, which has its base common to the base of the second NPN transistor 13, is given as ##EQU3## The collector current I.sub.4 in the transistor 14 is thus ##EQU4##
Thus, the base current i.sub.B1 in the first PNP transistor 11, which has the emitter connected to the collector of the second PNP transistor 14, is ##EQU5##
The transistors 11 to 14 may be integrated on the same substrate so that they have the same operating characteristics and an equal current amplification factor h.sub.fe (h.sub.fe &gt;1). In this case, the base current i.sub.B1 in the first PNP transistor 11 is ##EQU6## that is, it is substantially equal to the base current i.sub.B2 through the first NPN transistor 12. Theoretically, this means that the input impedance Z.sub.in of the circuit of FIG. 3 is infinite. That is, the circuit of FIG. 3 is a high input impedance circuit. However, this circuit requires a bias circuit for providing a bias to the transistors 11 and 12. The bias circuit usually consists of the resistors R1 and R2 as shown in FIG. 3, so that it reduces the input impedance.